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HCF4035B
4 STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER
s s
s s
s
s s s s
s s
s s
4 STAGE CLOCKED SHIFT OPERATION SYNCHRONOUS PARALLEL ENTRY ON ALL 4 STAGES JK INPUTS ON FIRST STAGE ASYNCHRONOUS TRUE/COMPLEMENT CONTROL ON ALL OUTPUTS STATIC FLIP-FLOP OPERATION; MASTER-SLAVE CONFIGURATION BUFFERED INPUTS AND OUTPUTS HIGH SPEED 12MHz (Typ.) at VDD = 10V QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4035BEY HCF4035BM1 T&R HCF4035M013TR
DESCRIPTION The HCF4035B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is a four stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK logic. Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial PIN CONNECTION
mode (PARALLEL/SERIAL control low). Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high. In the parallel or serial mode information is transferred on positive clock transitions. When the TRUE/ COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. The TRUE/ COMPLEMENT control functions asynchronously with respect to the CLOCK signal. JK input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence generation applications. With JK inputs connected together, the first stage becomes a D flip-flop. An asynchronous common RESET is also provided.
September 2001
1/11
HCF4035B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 9, 10, 11, 12 SYMBOL NAME AND FUNCTION Parallel Inputs True/Complement Outputs Reset Input Serial Inputs Clock Input Parallel/Serial Control True/Complement Control Negative Supply Voltage Positive Supply Voltage
PI-1 to PI-4 Q1/Q1 to Q4/ 1, 15, 14, 13 Q4 5 RESET 4, 3 J, K 6 CLOCK 7 P/S 2 T/C VSS 8 16 VDD
FUNCTIONAL DIAGRAM
TRUTH TABLE
tn-1 (Inputs) CLOCK J L H X H X X X
X : Don't Care
tn (Outputs) R L L L L L L H Qn-1 L L H Qn-1 H Qn-1 X Qn L H L Qn-1 Toggle Mode H Qn-1 L
K X X L L H X X
X
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HCF4035B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
3/11
HCF4035B
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 0.1 7.5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA A pF
II CI
Any Input Any Input
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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HCF4035B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 250 100 75 100 50 40 4 12 16 100 45 30 15 15 15 110 40 30 70 25 20 230 100 80 125 55 40 Max. 500 200 150 200 100 80 Unit
CLOCKED OPERATION tPLH tPHL Propagation Delay Time
ns
tTHL tTLH Transition Time
ns
fMAX
Maximum Clock Input Frequency Clock Pulse Width
2 6 8
MHz 200 90 60
tW
ns
tr , tf
Clock Input Rise or Fall Time Data Setup Time J/K lines
s 220 80 60 140 50 40 460 200 160 250 110 40
tsetup
ns
tsetup
Data Setup Time Parallel In Lines
ns
RESET OPERATION tPLH tPHL Propagation Delay Time
ns
tW
Reset Pulse Width
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
5/11
HCF4035B
TYPICAL APPLICATIONS Binary To BCD Converter
Bidec Logic
6/11
HCF4035B
DOUBLE SEQUENCE GENERATOR STATE SEQUENCES Using a control line (E) two different state sequences can be generated. For example, suppose the following two sequences are desiderated on command (control line E)
Control = E = 0 Q1 A 0 1 2 5 10 4 9 3 6 13 11 7 14 12 8 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 Q2 B 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 Q3 C 0 0 0 1 0 1 0 0 1 1 0 1 1 1 0 Q4 D 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 15 14 13 10 5 11 6 12 9 2 4 8 1 3 7 Q1 A 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 Q2 B 1 0 0 1 0 1 1 0 0 1 0 0 0 1 1 Q3 C 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 Q4 D 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0
SHIFT LEFT/SHIFT RIGHT REGISTER
7/11
HCF4035B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
8/11
HCF4035B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
9/11
HCF4035B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
10/11
HCF4035B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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